/*
 * Copyright 2015-2017, NVIDIA Corporation
 * Copyright 2019, Data61, CSIRO (ABN 41 687 119 230)
 *
 * SPDX-License-Identifier: GPL-2.0-only
 */

/*
 * The mux pad register offsets are taken from NVIDIA's L4T kernel sources.
 */

#pragma once

/* We only map in the first part of the pinctrl, the rest are AON-related and
 * we do not manage those pads. */
#define TX2_MUX_PADDR 0x2430000
#define TX2_MUX_SIZE  0x12000

enum mux_feature {
    MUX_FEATURE_UARTA,
    MUX_FEATURE_UARTB,
    //MUX_FEATURE_UARTC, pins are managed by the AON GPIO controller
    MUX_FEATURE_UARTD,

    MUX_FEATURE_SPI1,
    //MUX_FEATURE_SPI2, pins are managed by the AON GPIO controller
    MUX_FEATURE_SPI3,
    MUX_FEATURE_SPI4,

    /* Can't seem to MUX I2C4, I2C6, */
    MUX_FEATURE_I2C1,
    //MUX_FEATURE_I2C2, pins are managed by the AON GPIO controller
    MUX_FEATURE_I2C3,
    //MUX_FEATURE_I2C5, pins are managed by the AON GPIO controller
    MUX_FEATURE_I2C7,
    //MUX_FEATURE_I2C8, pins are managed by the AON GPIO controller
    MUX_FEATURE_I2C9,

    MUX_FEATURE_EQOS_RX,
    MUX_FEATURE_EQOS_TX,
    MUX_FEATURE_EQOS_MDIO,

    /* TODO More GPIOs.
     * Technically all pads can be used as GPIOs and not SFIOs.
     * So adding another GPIO would be just adding more one pin pingroups. */
    MUX_FEATURE_GPIO_PJ0,
    MUX_FEATURE_GPIO_PJ1,
    MUX_FEATURE_GPIO_PJ2,
    MUX_FEATURE_GPIO_PJ3,
    MUX_FEATURE_GPIO_PJ4,
    MUX_FEATURE_GPIO_PJ5,
    MUX_FEATURE_GPIO_PJ6,

    NMUX_FEATURES
};

/* Each pad contains two sets of 32-bit sized registers,
 * the control and the drive strength register.
 * These offsets describes the offsets of the control register. */
typedef enum mux_pad {
    MUX_PAD_EXTPERIPH2_CLK_PO1 = 0x0000,
    MUX_PAD_EXTPERIPH1_CLK_PO0 = 0x0008,
    MUX_PAD_CAM_I2C_SDA_PO3 = 0x0010,
    MUX_PAD_CAM_I2C_SCL_PO2 = 0x0018,
    MUX_PAD_GPIO_CAM1_PN0 = 0x0020,
    MUX_PAD_GPIO_CAM2_PN1 = 0x0028,
    MUX_PAD_GPIO_CAM3_PN2 = 0x0030,
    MUX_PAD_GPIO_CAM4_PN3 = 0x0038,
    MUX_PAD_GPIO_CAM5_PN4 = 0x0040,
    MUX_PAD_GPIO_CAM6_PN5 = 0x0048,
    MUX_PAD_GPIO_CAM7_PN6 = 0x0050,
    MUX_PAD_GPIO_AUD3_PK0 = 0x1000,
    MUX_PAD_GPIO_AUD2_PJ7 = 0x1008,
    MUX_PAD_GPIO_AUD1_PJ6 = 0x1010,
    MUX_PAD_GPIO_AUD0_PJ5 = 0x1018,
    MUX_PAD_AUD_MCLK_PJ4 = 0x1020,
    MUX_PAD_DAP1_FS_PJ3 = 0x1028,
    MUX_PAD_DAP1_DIN_PJ2 = 0x1030,
    MUX_PAD_DAP1_DOUT_PJ1 = 0x1038,
    MUX_PAD_DAP1_SCLK_PJ0 = 0x1040,
    MUX_PAD_DMIC1_CLK_PM1 = 0x2000,
    MUX_PAD_DMIC1_DAT_PM0 = 0x2008,
    MUX_PAD_DMIC2_DAT_PM2 = 0x2010,
    MUX_PAD_DMIC2_CLK_PM3 = 0x2018,
    MUX_PAD_DMIC4_DAT_PM4 = 0x2020,
    MUX_PAD_DMIC4_CLK_PM5 = 0x2028,
    MUX_PAD_DAP4_FS_PCC3 = 0x2030,
    MUX_PAD_DAP4_DIN_PCC2 = 0x2038,
    MUX_PAD_DAP4_DOUT_PCC1 = 0x2040,
    MUX_PAD_DAP4_SCLK_PCC0 = 0x2048,
    MUX_PAD_GPIO_PQ0_PI0 = 0x3000,
    MUX_PAD_GPIO_PQ1_PI1 = 0x3008,
    MUX_PAD_GPIO_PQ2_PI2 = 0x3010,
    MUX_PAD_GPIO_PQ3_PI3 = 0x3018,
    MUX_PAD_GPIO_PQ4_PI4 = 0x3020,
    MUX_PAD_GPIO_PQ5_PI5 = 0x3028,
    MUX_PAD_GPIO_PQ6_PI6 = 0x3030,
    MUX_PAD_GPIO_PQ7_PI7 = 0x3038,
    MUX_PAD_DAP2_DIN_PC3 = 0x4000,
    MUX_PAD_DAP2_DOUT_PC2 = 0x4008,
    MUX_PAD_DAP2_FS_PC4 = 0x4010,
    MUX_PAD_DAP2_SCLK_PC1 = 0x4018,
    MUX_PAD_UART4_CTS_PB3 = 0x4020,
    MUX_PAD_UART4_RTS_PB2 = 0x4028,
    MUX_PAD_UART4_RX_PB1 = 0x4030,
    MUX_PAD_UART4_TX_PB0 = 0x4038,
    MUX_PAD_GPIO_WAN4_PC0 = 0x4040,
    MUX_PAD_GPIO_WAN3_PB6 = 0x4048,
    MUX_PAD_GPIO_WAN2_PB5 = 0x4050,
    MUX_PAD_GPIO_WAN1_PB4 = 0x4058,
    MUX_PAD_GEN1_I2C_SCL_PC5 = 0x4060,
    MUX_PAD_GEN1_I2C_SDA_PC6 = 0x4068,
    MUX_PAD_UART1_CTS_PT3 = 0x5000,
    MUX_PAD_UART1_RTS_PT2 = 0x5008,
    MUX_PAD_UART1_RX_PT1 = 0x5010,
    MUX_PAD_UART1_TX_PT0 = 0x5018,
    MUX_PAD_DIRECTDC1_OUT3_PQ5 = 0x5028,
    MUX_PAD_DIRECTDC1_OUT2_PQ4 = 0x5030,
    MUX_PAD_DIRECTDC1_OUT1_PQ3 = 0x5038,
    MUX_PAD_DIRECTDC1_OUT0_PQ2 = 0x5040,
    MUX_PAD_DIRECTDC1_IN_PQ1 = 0x5048,
    MUX_PAD_DIRECTDC1_CLK_PQ0 = 0x5050,
    MUX_PAD_DIRECTDC_COMP = 0x5058,
    MUX_PAD_SDMMC4_COMP = 0x6000, // Not listed in the L4T but is in the manual.
    MUX_PAD_SDMMC4_CLK = 0x6004,
    MUX_PAD_SDMMC4_CMD = 0x6008,
    MUX_PAD_SDMMC4_DQS = 0x600c,
    MUX_PAD_SDMMC4_DAT7 = 0x6010,
    MUX_PAD_SDMMC4_DAT6 = 0x6014,
    MUX_PAD_SDMMC4_DAT5 = 0x6018,
    MUX_PAD_SDMMC4_DAT4 = 0x601c,
    MUX_PAD_SDMMC4_DAT3 = 0x6020,
    MUX_PAD_SDMMC4_DAT2 = 0x6024,
    MUX_PAD_SDMMC4_DAT1 = 0x6028,
    MUX_PAD_SDMMC4_DAT0 = 0x602c,
    MUX_PAD_PEX_L2_CLKREQ_N_PA6 = 0x7000,
    MUX_PAD_PEX_WAKE_N_PA2 = 0x7008,
    MUX_PAD_PEX_L1_CLKREQ_N_PA4 = 0x7010,
    MUX_PAD_PEX_L1_RST_N_PA3 = 0x7018,
    MUX_PAD_PEX_L0_CLKREQ_N_PA1 = 0x7020,
    MUX_PAD_PEX_L0_RST_N_PA0 = 0x7028,
    MUX_PAD_PEX_L2_RST_N_PA5 = 0x7030,
    MUX_PAD_SDMMC1_CLK_PD0 = 0x8000,
    MUX_PAD_SDMMC1_CMD_PD1 = 0x8008,
    MUX_PAD_SDMMC1_COMP = 0x8010,
    MUX_PAD_SDMMC1_DAT3_PD5 = 0x8014,
    MUX_PAD_SDMMC1_DAT2_PD4 = 0x801c,
    MUX_PAD_SDMMC1_DAT1_PD3 = 0x8024,
    MUX_PAD_SDMMC1_DAT0_PD2 = 0x802c,
    MUX_PAD_EQOS_TD3_PE4 = 0x9000,
    MUX_PAD_EQOS_TD2_PE3 = 0x9008,
    MUX_PAD_EQOS_TD1_PE2 = 0x9010,
    MUX_PAD_EQOS_TD0_PE1 = 0x9018,
    MUX_PAD_EQOS_RD3_PF1 = 0x9020,
    MUX_PAD_EQOS_RD2_PF0 = 0x9028,
    MUX_PAD_EQOS_RD1_PE7 = 0x9030,
    MUX_PAD_EQOS_MDIO_PF4 = 0x9038,
    MUX_PAD_EQOS_RD0_PE6 = 0x9040,
    MUX_PAD_EQOS_MDC_PF5 = 0x9048,
    MUX_PAD_EQOS_COMP = 0x9050,
    MUX_PAD_EQOS_TXC_PE0 = 0x9054,
    MUX_PAD_EQOS_RXC_PF3 = 0x905c,
    MUX_PAD_EQOS_TX_CTL_PE5 = 0x9064,
    MUX_PAD_EQOS_RX_CTL_PF2 = 0x906c,
    MUX_PAD_SDMMC3_DAT3_PG5 = 0xa000,
    MUX_PAD_SDMMC3_DAT2_PG4 = 0xa008,
    MUX_PAD_SDMMC3_DAT1_PG3 = 0xa010,
    MUX_PAD_SDMMC3_DAT0_PG2 = 0xa018,
    MUX_PAD_SDMMC3_COMP = 0xa020,
    MUX_PAD_SDMMC3_CMD_PG1 = 0xa024,
    MUX_PAD_SDMMC3_CLK_PG0 = 0xa02c,
    MUX_PAD_QSPI_IO3_PR4 = 0xb000,
    MUX_PAD_QSPI_IO2_PR3 = 0xb008,
    MUX_PAD_QSPI_IO1_PR2 = 0xb010,
    MUX_PAD_QSPI_IO0_PR1 = 0xb018,
    MUX_PAD_QSPI_SCK_PR0 = 0xb020,
    MUX_PAD_QSPI_CS_N_PR5 = 0xb028,
    MUX_PAD_QSPI_COMP = 0xb030,
    MUX_PAD_GPIO_WAN8_PH3 = 0xd000,
    MUX_PAD_GPIO_WAN7_PH2 = 0xd008,
    MUX_PAD_GPIO_WAN6_PH1 = 0xd010,
    MUX_PAD_GPIO_WAN5_PH0 = 0xd018,
    MUX_PAD_UART2_TX_PX0 = 0xd020,
    MUX_PAD_UART2_RX_PX1 = 0xd028,
    MUX_PAD_UART2_RTS_PX2 = 0xd030,
    MUX_PAD_UART2_CTS_PX3 = 0xd038,
    MUX_PAD_UART5_RX_PX5 = 0xd040,
    MUX_PAD_UART5_TX_PX4 = 0xd048,
    MUX_PAD_UART5_RTS_PX6 = 0xd050,
    MUX_PAD_UART5_CTS_PX7 = 0xd058,
    MUX_PAD_GPIO_MDM1_PY0 = 0xd060,
    MUX_PAD_GPIO_MDM2_PY1 = 0xd068,
    MUX_PAD_GPIO_MDM3_PY2 = 0xd070,
    MUX_PAD_GPIO_MDM4_PY3 = 0xd078,
    MUX_PAD_GPIO_MDM5_PY4 = 0xd080,
    MUX_PAD_GPIO_MDM6_PY5 = 0xd088,
    MUX_PAD_GPIO_MDM7_PY6 = 0xd090,
    MUX_PAD_BCPU_PWR_REQ_PH4 = 0xd098,
    MUX_PAD_MCPU_PWR_REQ_PH5 = 0xd0a0,
    MUX_PAD_GPU_PWR_REQ_PH6 = 0xd0a8,
    MUX_PAD_GEN7_I2C_SCL_PL0 = 0xd0b0,
    MUX_PAD_GEN7_I2C_SDA_PL1 = 0xd0b8,
    MUX_PAD_GEN9_I2C_SDA_PL3 = 0xd0c0,
    MUX_PAD_GEN9_I2C_SCL_PL2 = 0xd0c8,
    MUX_PAD_USB_VBUS_EN0_PL4 = 0xd0d0,
    MUX_PAD_USB_VBUS_EN1_PL5 = 0xd0d8,
    MUX_PAD_GP_PWM7_PL7 = 0xd0e0,
    MUX_PAD_GP_PWM6_PL6 = 0xd0e8,
    MUX_PAD_GPIO_EDP2_PP5 = 0x10000,
    MUX_PAD_GPIO_EDP3_PP6 = 0x10008,
    MUX_PAD_GPIO_EDP0_PP3 = 0x10010,
    MUX_PAD_GPIO_EDP1_PP4 = 0x10018,
    MUX_PAD_DP_AUX_CH0_HPD_PP0 = 0x10020,
    MUX_PAD_DP_AUX_CH1_HPD_PP1 = 0x10028,
    MUX_PAD_HDMI_CEC_PP2 = 0x10030,
    MUX_PAD_UFS0_RST_PBB1 = 0x11000,
    MUX_PAD_UFS0_REF_CLK_PBB0 = 0x11008,
} mux_pad_t;

/* Offsets for the other block of pinmux registers, starting from 0xc3010000.
 * We don't currently use these pins for the mux features that we support,
 * but just leave them here so someone doesn't have to go through the effort.
typedef enum mux_pad_aux {,
    gpio_sw1_pff1 = = 0x1000,
    gpio_sw2_pff2 = = 0x1008,
    gpio_sw3_pff3 = = 0x1010,
    gpio_sw4_pff4 = = 0x1018,
    shutdown = = 0x1020,
    pmu_int = = 0x1028,
    safe_state_ps3 = = 0x1030,
    vcomp_alert_ps4 = = 0x1038,
    soc_pwr_req = = 0x1040,
    batt_oc_ps2 = 0x1048,
    clk_32k_in = 0x1050,
    power_on_pff0 = = 0x1058,
    pwr_i2c_scl_ps0 = 0x1060,
    pwr_i2c_sda_ps1 = 0x1068,
    gpio_dis0_pu0 = 0x1080 ,
    gpio_dis1_pu1 = 0x1088,
    gpio_dis2_pu2 = 0x1090,
    gpio_dis3_pu3 = 0x1098,
    gpio_dis4_pu4 = 0x10a0,
    gpio_dis5_pu5 = 0x10a8,
    touch_clk_pee2 = 0x2000,
    uart3_cts_pw5 = 0x2008,
    uart3_rts_pw4 = 0x2010,
    uart3_rx_pw3 = 0x2018,
    uart3_tx_pw2 = 0x2020,
    gen8_i2c_sda_pw1 = 0x2028,
    gen8_i2c_scl_pw0 = 0x2030,
    uart7_rx_pw7 = 0x2038,
    uart7_tx_pw6 = 0x2040,
    gpio_sen0_pv0 = 0x2048,
    gpio_sen1_pv1 = 0x2050,
    gpio_sen2_pv2 = 0x2058,
    gpio_sen3_pv3 = 0x2060,
    gpio_sen4_pv4 = 0x2068,
    gpio_sen5_pv5 = 0x2070,
    gpio_sen6_pv6 = 0x2078,
    gpio_sen7_pv7 = 0x2080,
    gpio_sen8_pee0 = 0x2088,
    gpio_sen9_pee1 = 0x2090,
    can_gpio7_paa7 = 0x3000,
    can1_dout_pz0 = 0x3008,
    can1_din_pz1 = 0x3010,
    can0_dout_pz2 = 0x3018,
    can0_din_pz3 = 0x3020,
    can_gpio0_paa0 = 0x3028,
    can_gpio1_paa1 = 0x3030,
    can_gpio2_paa2 = 0x3038,
    can_gpio3_paa3 = 0x3040,
    can_gpio4_paa4 = 0x3048,
    can_gpio5_paa5 = 0x3050,
    can_gpio6_paa6 = 0x3058,
} mux_pad_aux_t;
*/
